1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication process therefor. More particularly, the invention relates to a semiconductor memory device including a NOR-type flash EEPROM in which the impurity concentration in a portion of a channel region adjacent to source/drain regions is different from that in the other portion of the channel region, and to a fabrication process therefor.
2. Description of Related Art
Flash EEPROMs of one-transistor-per-cell structure are conventionally used as nonvolatile memory devices which are capable of electrically writing and erasing data.
A memory cell transistor in such a flash EEPROM includes, as shown in FIG. 10, a floating gate 23 of a polysilicon film formed on a semiconductor substrate 21 with intervention of a gate insulating film 22, an ONO insulating film 24, and a control gate 27 comprised of a polysilicon film 25 and a tungsten silicide film 26 and also serving as a word line. Source/drain regions 28 and 29 are formed on opposite sides of the floating gate 23 and the control gate 27, and the source region 28 has a low-concentration impurity layer 28a in its peripheral portion.
A fabrication process for a memory cell transistor as described above will hereinafter be described.
As shown in FIG. 8, P-type ions are implanted into a device formation region of a P-type semiconductor substrate 21 having a device isolation film (not shown) to control the impurity concentration in a channel region, and then a silicon oxide film 22 is formed on the semiconductor substrate 21.
In turn, as shown in FIG. 9, a floating gate 23, an insulating film 24 and a control gate 27 comprised of a polysilicon film 25 and a tungsten silicide film 26 are formed on the resulting substrate. A resist pattern 30 having an opening only on a source formation region is formed on the resulting substrate by a photolithographic and etching process. Then, a low-concentration impurity layer 28a is formed by implanting N-type ions (N.sup.+) in a low concentration into the resulting substrate with use of the floating gate 23, the control gate 27 and the resist pattern 30 as a mask.
Subsequently, the resist pattern 30 is removed, and N-type ions (N.sup.++) are implanted in a high concentration into the resulting semiconductor substrate 21 including the floating gate 23 and the control gate 27 to form source/drain regions 28 and 29.
To write data to the memory cell transistor shown in FIG. 10, a high voltage of about 12 V is applied to the control gate with the source grounded, and a voltage of about 7 V is applied to the drain. At this time, a large current flows between the drain and the source, whereby hot electrons of a high energy generated around the drain junction are injected into the floating gate and accumulated in the floating gate. The memory cell transistor to which data is written has a high threshold voltage, thereby storing therein data "0", for example.
To erase data stored in the memory cell transistor, on the other hand, a high voltage of about 12 V is applied to the source with the control gate (positive gate type) grounded. At this time, a high-intensity electric field is generated between the floating gate and the source, and the electrons accumulated in the floating gate are drawn through the thin silicon oxide film by a tunnel current. Therefore, the threshold of the memory cell transistor is reduced, so that the data stored therein is erased.
In the memory cell transistor of FIG. 10, the data writing is performed on the drain junction side, and the data erasing is performed on the source junction side. In a device design, the junction profile is optimized in accordance with the operations on the drain junction side and the source junction side. More specifically, an electric-field-concentration type profile involving an abrupt change in the impurity concentration is employed on the drain junction side to increase the writing efficiency, while an electric-field-dispersion type profile involving a stepwise change in the impurity concentration is employed on the source junction side to allow the application of a high-intensity electric field for data erasing. Therefore, the construction is asymmetrical on the drain junction side and on the source junction side.
In a method for reducing a voltage to be applied to the source for data erasing, a negative voltage is applied to the control gate (negative gate type).
In the memory cell transistor of FIG. 10, the ion concentration around a channel inversion layer is rendered substantially uniform by implanting ions of the same conductivity type as that of the semiconductor substrate 21 before the formation of the floating gate 23. If the impurity concentration in the channel inversion layer is uniformly increased along the length of the channel, the efficiency of hot electron injection into the floating gate for data writing is increased, that is, the time required for the data writing can be shortened. When electrons are drawn out of the floating gate to the source for data erasing, however, a band-to-band tunneling current increases causing increase in current consumption. In addition, hot holes thereby generated migrate into the tunnel oxide film, so that hot hole behavior becomes less reliable for channel operation.
On the other hand, if the impurity concentration in the channel inversion layer is uniformly reduced along the length of the channel, the band-to-band tunneling current can be reduced, but the efficiency of data writing is reduced. Therefore, a tradeoff between the writing characteristics and the erasing characteristics is a critical problem.
To solve this problem, a memory cell transistor is proposed in which the impurity concentrations in a portion adjacent to a source region and in a portion adjacent to a drain region are independently optimized by implanting ions of the same conductivity type as that of a semiconductor substrate only into the portion adjacent to the drain region after the aforesaid process steps for memory cell transistor fabrication are performed.
However, the fabrication process for such a memory cell transistor requires an additional mask for ion implantation for the optimization of the impurity concentration in the portion adjacent to the drain region. In addition, the fabrication process requires a resist application step, an exposure step, a developing step, a removal step and an impurity-diffusion-layer formation step. Thus, the process is complicated, resulting in a reduced throughput.
One exemplary fabrication process for a memory cell transistor having source/drain regions of an asymmetrical structure is disclosed in Japanese Unexamined Patent Publication No. 4-329632 (1992). As shown in FIG. 11, gate electrodes 33 formed on a first region A of a semiconductor substrate 31 are spaced from each other a predetermined distance, and gate electrodes 33 on a second region B of the semiconductor substrate 31 are spaced from each other a distance smaller than that in the first region A. Ions are implanted into the first and second regions A and B at an ion implantation angle .theta..sub.1 (0.degree.&lt;.theta..sub.1 &lt;90.degree.) with respect to a normal line to the semiconductor substrate 31 by oblique rotation ion implantation to form source/drain regions 34A in the first region A and source/drain regions 34B in the second region B respectively having different ion concentrations.
Another exemplary fabrication process is disclosed in Japanese Unexamined Patent Publication No. 6-21476 (1994). As shown in FIGS. 12(a) to 12(d), P-type ions are implanted from the side of a drain (FIG. 12(b)) and N-type ions are implanted from the side of a source (FIG. 12(c)) at an ion implantation angle .theta..sub.2 (0.degree.&lt;.theta..sub.2 &lt;90.degree.).
However, the aforesaid ion implantation methods cannot be applied to a NOR-type flash EEPROM such as of FIG. 10 having a common source region shared with adjacent memory cells, because ions to be selectively implanted into the drain region are also implanted into the source region, making it impossible to form a desired flash EEPROM of the asymmetrical structure.